1. Field of the Invention
The present invention relates to semiconductor fabrication, particularly to a method for removing spacers in semiconductor fabrication.
2. Description of the Prior Art
Semiconductor device geometries have dramatically decreased in size since such devices were first introduced several decades ago. Today's fabrication plants are producing devices having 0.35 μm, 90 nm, and even 65 nm feature sizes or smaller. As geometries shrink, semiconductor manufacturing methods often need to be improved.
Conventional MOS (metal-oxide-semiconductor) device fabrication utilizes a technique of building material spacers to help control and define the implantation of dopants in the source and drain regions of the MOS. A conventional NMOS semiconductor device is schematically illustrated in FIG. 1. The conventional NMOS transistor device 10 generally includes a semiconductor substrate generally comprising a silicon layer 16 having a source 18 and a drain 20 separated by a channel region 22. Ordinarily, the source 18 and drain 20 further border a shallow-junction source extension 17 and a shallow-junction drain extension 19, respectively. A thin oxide layer 14 separates a gate 12, generally comprising polysilicon, from the channel region 22. The source 18 and drain 20 are N+ regions having been doped by arsenic, antimony or phosphorous. The channel region 22 is generally boron doped. A silicon nitride spacer 32 is formed on sidewalls of the gate 12. A liner 30, generally comprising silicon dioxide, is interposed between the gate 12 and the silicon nitride spacer 32. A salicide layer 42 is selectively formed on the exposed silicon surface of the device 10. The process known as self-aligned silicide (salicide) process has been widely utilized to fabricate metal silicide materials, in which a source/drain region is first formed, a metal layer comprised of cobalt, titanium, or nickel is disposed on the source/drain region and the gate structure, and a rapid thermal process (RTP) is performed to react the metal layer with the silicon contained within the gate structure and the source/drain region to form a metal silicide for reducing the sheet resistance of the source/drain region.
In the conventional MOS fabrication technique, spacers are often used in the fabrication of LDD (lightly doped drain) regions to facilitate the different levels of doping for the drain/source regions and the LDD regions. The LDD region can be controlled by the lateral spacer dimension and the thermal drive cycle, and can be independent from the source and drain implant depth. In the 65 nm technology and beyond, the channel mobility enhancement can be further achieved by deposition of a highly strained dielectric layer after spacer removal. However, removing the spacer, especially spacer SiN (silicon nitride), is critical because removal can damage adjacent structures, such as the metal silicide layer, the gate, and the underlying silicon substrate.
Conventionally, the spacer SiN is removed using a hot H3PO4 process at a temperature of 160° C., as the step 100 shows in FIG. 2. This often leads to the erosion of NiSi substrate and NiSi polycide in the PMOS and NMOS regions. While, at low temperatures, phosphoric acid is unable to significantly etch the silicon nitride, higher temperatures speed up the attack of the silicon oxide, but decrease the etch rate of the silicon nitride. As a result, it has been difficult to etch a silicon nitride structure using phosphoric acid.
Therefore, there is a need for a better method to remove spacers and not damage salicide layers.